Show simple item record

dc.contributor.advisorArslan, Tughrul
dc.contributor.advisorThompson, John
dc.contributor.authorKhan, Zahid
dc.date.accessioned2012-01-25T13:53:27Z
dc.date.available2012-01-25T13:53:27Z
dc.date.issued2011-11-22
dc.identifier.urihttp://hdl.handle.net/1842/5784
dc.description.abstractThis thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom ASIC for power optimization and LDPC is implemented on dynamically reconfigurable fabric for both power and performance optimization. Both MIMO and LDPC are considered computational bottlenecks of current and future wireless standards such as IEEE 802.11n for Wi-Fi and IEEE 802.16 for WiMax applications. Optimization of these algorithms is carried out separately. The thesis is organized implicitly in two parts. The first part presents selection and analysis of the VBLAST receiver used in MIMO wireless system from custom ASIC perspective and identifies those processing elements that consume larger area as well as power due to complex signal processing. The thesis models a scalable VBLAST architecture based on MMSE nulling criteria assuming block rayleigh flat fading channel. After identifying the major area and power consuming blocks, it proposes low power and area efficient VLSI architectures for the three building blocks of VBLAST namely Pseudo Inverse, Sorting and NULLing & Cancellation modules assuming a 4x4 MIMO system. The thesis applies dynamic power management, algebraic transformation (strength reduction), resource sharing, clock gating, algorithmic modification, operation substitution, redundant arithmetic and bus encoding as the low power techniques applied at different levels of design abstraction ranging from system to architecture, to reduce power consumption. It also presents novel architectures not only for the constituent blocks but also for the whole receiver. It builds the low power VBLAST receiver for single carrier and provides its area, power and performance figures. It then investigates into the practicality and feasibility of VBLAST into an OFDM environment. It provides estimated data with respect to silicon real estate and throughput from which conclusion can easily be drawn about the feasibility of VBLAST in a multi carrier environment. The second part of the thesis presents novel architectures for the real time adaptive LDPC encoder and decoder as specified in IEEE 802.16E standard for WiMax application. It also presents optimizations of encoder as well as decoder on RICA (Reconfigurable Instruction Cell Architecture). It has searched an optimized way of storing the H matrices that reduces the memory by 20 times. It uses Loop unrolling to distribute the instructions spatially depending upon the available resources to execute them concurrently to as much as possible. The parallel memory banks and distributed registers inside RICA allow good reduction in memory access time. This together with hardware pipelining provides substantial potential for optimizing algorithms from power and performance perspectives. The thesis also suggests ways of improvements inside RICA architecture.en
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionZ. Khan, T. Arslan, J. S. Thompson, A. T. Erdogan, “Analysis and Implementation of Multiple–Input, Multiple–Output VBLAST Receiver From Area and Power Efficiency”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Nov. 2006, Volume: 14, Issue:11 On page(s): 1281-1286en
dc.relation.hasversionZ. Khan, T. Arslan, “Performance of IEEE defined LDPC Codes under Various decoding algorithms and their implementation on a Reconfigurable Instruction Cell Architecture”, submitted to AHS 2007 conference.en
dc.relation.hasversionZ. Khan and T. Arslan, “Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture” accepted for publication in DATE 2007 to be held in France.en
dc.relation.hasversionZ. Khan, T. Arslan, J.S. Thompson, A.T. Erdogan, “A New Pipelined Implementation for Minimum Norm Sorting used in Square Root Algorithm for MIMO-VBLAST Systems” accepted for publication in DATE 2007 to be held in France.en
dc.relation.hasversionZ. Khan and T. Arslan, “Implementation of a Real-Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture”, accepted for publication in ASP-DAC 2007 held in Japanen
dc.relation.hasversionZ. Khan, T.Arslan, J. S. Thompson, A.T.Erdogan, “A low power implementation of Minimum Norm Sorting and block upper triangularization of matrices used in MIMO Wireless Systems”, accepted for publication in IEEE- VLSI Design Conference held in Banglore India in Jan 2007.en
dc.relation.hasversionZ. Khan and T. Arslan, “A New Real-Time Programmable Encoder for Low Density Parity Check Code Targeting a Reconfigurable Instruction Cell Architecture”, accepted for publication in 2006 IEEE International Conference on Field Programmable Technology, 13-15 December 2006, Bangkok, Thailand.en
dc.relation.hasversionZahid Khan, Tughrul Arslan, Scott MacDougall, “A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 standard and its efficient Implementation on a DSP Processor” accepted for presentation in the IEEESOCC conference to be held in Texas, Austin in September 2006. This is joint work with Freescale Semiconductor Ltd.en
dc.relation.hasversionahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan, “Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System” IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), Karlsruhe, Germany, March 2-3, 2006en
dc.relation.hasversionZahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan, “Area & Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System” 19th International Conference on VLSI Design (VLSI Design 2006), pp. 734-737, Hyderabad, India, January 3 - 7, 2006.en
dc.subjectMIMOen
dc.subjectLDPCen
dc.subjectlow poweren
dc.subjectVBLASTen
dc.titleOptimization of advanced telecommunication algorithms from power and performance perspectiveen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


Files in this item

This item appears in the following Collection(s)

Show simple item record