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dc.contributor.advisorTopham, Nigel
dc.contributor.authorZuluaga, Marcela
dc.date.accessioned2011-01-18T14:10:18Z
dc.date.available2011-01-18T14:10:18Z
dc.date.issued2010
dc.identifier.urihttp://hdl.handle.net/1842/4630
dc.description.abstractCustomization of processors with instruction set extensions (ISEs) is a technique that improves performance through parallelization with a reasonable area overhead, in exchange for additional design effort. This thesis presents a collection of novel techniques that reduce the design effort and cost of generating ISEs by advancing automation and reconfigurability. In addition, these techniques maximize the perfomance gained as a function of the additional commited resources. Including ISEs into a processor design implies development at many levels. Most prior works on ISEs solve separate stages of the design: identification, selection, and implementation. However, the interations between these stages also hold important design trade-offs. In particular, this thesis addresses the lack of interaction between the hardware implementation stage and the two previous stages. Interaction with the implementation stage has been mostly limited to accurately measuring the area and timing requirements of the implementation of each ISE candidate as a separate hardware module. However, the need to independently generate a hardware datapath for each ISE limits the flexibility of the design and the performance gains. Hence, resource sharing is essential in order to create a customized unit with multi-function capabilities. Previously proposed resource-sharing techniques aggressively share resources amongst the ISEs, thus minimizing the area of the solution at any cost. However, it is shown that aggressively sharing resources leads to large ISE datapath latency. Thus, this thesis presents an original heuristic that can be parameterized in order to control the degree of resource sharing amongst a given set of ISEs, thereby permitting the exploration of the existing implementation trade-offs between instruction latency and area savings. In addition, this thesis introduces an innovative predictive model that is able to quickly expose the optimal trade-offs of this design space. Compared to an exhaustive exploration of the design space, the predictive model is shown to reduce by two orders of magnitude the number of executions of the resource-sharing algorithm that are required in order to find the optimal trade-offs. This thesis presents a technique that is the first one to combine the design spaces of ISE selection and resource sharing in ISE datapath synthesis, in order to offer the designer solutions that achieve maximum speedup and maximum resource utilization using the available area. Optimal trade-offs in the design space are found by guiding the selection process to favour ISE combinations that are likely to share resources with low speedup losses. Experimental results show that this combined approach unveils new trade-offs between speedup and area that are not identified by previous selection techniques; speedups of up to 238% over previous selection thecniques were obtained. Finally, multi-cycle ISEs can be pipelined in order to increase their throughput. However, it is shown that traditional ISE identification techniques do not allow this optimization due to control flow overhead. In order to obtain the benefits of overlapping loop executions, this thesis proposes to carefully insert loop control flow statements into the ISEs, thus allowing the ISE to control the iterations of the loop. The proposed ISEs broaden the scope of instruction-level parallelism and obtain higher speedups compared to traditional ISEs, primarily through pipelining, the exploitation of spatial parallelism, and reducing the overhead of control flow statements and branches. A detailed case study of a real application shows that the proposed method achieves 91% higher speedups than the state-of-the-art, with an area overhead of less than 8% in hardware implementation.en
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionMarcela Zuluaga and Nigel Topham. “Resource Sharing in Custom Instruction-set Extensions”. In: Proceedings of the 6th IEEE Symposium Application specific Processors (SASP). June 2008.en
dc.relation.hasversionMarcela Zuluaga, Theo Kluter, Philip Brisk, Nigel Topham and Paolo Ienne. “Introducing Control-flow Inclusion to Support Pipelining in Custom Instruction-set Extensions”. In: Proceedings of the 7th IEEE Symposium on Application-specific Processors (SASP). July 2009.en
dc.relation.hasversionMarcela Zuluaga and Nigel Topham. “Design-space Exploration of Resource-sharing Solutions for Custom Instruction-set Extensions”. In: IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD). December 2009.en
dc.relation.hasversionMarcela Zuluaga and Nigel Topham. “Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing ”. In: Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS). July 2010.en
dc.subjectinstruction set extensionsen
dc.subjectparallelizationen
dc.subjectprocessor designen
dc.titleEfficient design-space exploration of custom instruction-set extensionsen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


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