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dc.contributor.advisorArslan, Tughrul
dc.contributor.advisorErdogan, Ahmet
dc.contributor.authorLin, Ming-Lang
dc.date.accessioned2011-01-18T14:07:03Z
dc.date.available2011-01-18T14:07:03Z
dc.date.issued2010
dc.identifier.urihttp://hdl.handle.net/1842/4627
dc.description.abstractData conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs. Alternatively, in some applications such as speech, temperature sensor, etc. signals remain possibly unchanged for prolonged periods with brief bursts of significant activity. If trational ADCs are employed in such circumstances a higher bandwidth is required for transmitting the converted samples. On the other hand, sampling signals with an extremely high clock rate are also required for converting the signals with the feature of sparsity in time domain. The level-crossing sampling scheme (LCSS) is one of the data conversions suitable for converting signals with the sparsity feature and brief bursts of signigicant activity. due to the traditional LCSS with a fixed clock rate being limited in applications a novel irregular data conversion scheme called analogue-to-information system (AIS) is proposed in this thesis. The AIS is typically based upon LCSS, but an adjustable clock generator and a real time data compression scheme are applied to it. As the system-level simulations results of AIS show it can be seen that a data transmission saving rate nearly 30% is achieved for different signals. PLLs with fast pull-in and locking schemes are very important when they are applied in TDMA systems and fequency hopping wireless systems. So a novel triple path nonlinear phase frequency detector (TPNPFD) is also proposed in this thesis. Compared to otherPFDs, the pll-in and locking time in TPNPFD is much shorter. A proper transmission data format can make the recreation of the skipped samples and the reconstruction of the original signal more efficient, i.e. they can be achieved in a minimum number of the received data without increasing much more hardware complexity. So the preliminary data format used for transmitting the converted data from AIS is also given in the final chapter of this thesis for future works.en
dc.contributor.sponsorTatung Universityen
dc.language.isoenen
dc.publisherThe University of Edinburghen
dc.relation.hasversionMing-Lang Lin, Ahmet T. Erdogan, Arslan, T., Stoica, A. Reduced pull-in time of PLLS using a triple path PFD and a resistir scalar scheme. in Design & Technolgy of Integrated systems in Nanoscale Era, 2007. DTIS International Conference on 2007.en
dc.relation.hasversionMing-Lang Lin, Ahmet T. Erdogan, Arslan, T., Stoica, A. A fast pull-in scheme of plls using a triple path onolinear phase frequency detector, in SOC Conference, 2007 IEEE International 2007.en
dc.relation.hasversionMing-Lang Lin, Ahmet T. Erdogan, Arslan, T., Stoica, A. A novel CMOS exponential approximation circuit. in SOC Conference, 2008 IEEE International 2008.en
dc.relation.hasversionMing-Lang Lin, Ahmet T. Erdogan, Arslan, T., Stoica, A. A novel sampling scheme for efficient analogue to digital conversion. In Adaptive hardware and systems, 2007. AHS 2007. Second NASA/ESA Conference in 2007.en
dc.subjectirregular samplingen
dc.subjectphase-locked loopsen
dc.subjectfrequency synthesizeren
dc.titleAnalogue to information system based on PLL-based frequency synthesizers with fast locking schemesen
dc.typeThesis or Dissertationen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePhD Doctor of Philosophyen


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