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|Title: ||High speed simulation of microprocessor systems using LTU dynamic binary translation|
|Authors: ||Jones, Daniel|
|Supervisor(s): ||Topham, Nigel|
|Issue Date: ||2010|
|Publisher: ||The University of Edinburgh|
|Abstract: ||This thesis presents new simulation techniques designed to speed up the simulation
of microprocessor systems. The advanced simulation techniques may be applied to
the simulator class which employs dynamic binary translation as its underlying technology.
This research supports the hypothesis that faster simulation speeds can be
realized by translating larger sections of the target program at runtime. The primary
motivation for this research was to help facilitate comprehensive design-space exploration
and hardware/software co-design of novel processor architectures by reducing
the time required to run simulations.
Instruction set simulators are used to design and to verify new system architectures,
and to develop software in parallel with hardware. However, compromises must often
be made when performing these tasks due to time constraints. This is particularly true
in the embedded systems domain where there is a short time-to-market. The processing
demands placed on simulation platforms are exacerbated further by the need to simulate
the increasingly complex, multi-core processors of tomorrow. High speed simulators
are therefore essential to reducing the time required to design and test advanced
microprocessors, enabling new systems to be released ahead of the competition.
Dynamic binary translation based simulators typically translate small sections of the
target program at runtime. This research considers the translation of larger units of
code in order to increase simulation speed. The new simulation techniques identify
large sections of program code suitable for translation after analyzing a profile of the
target program’s execution path built-up during simulation.
The average instruction level simulation speed for the EEMBC benchmark suite is
shown to be at least 63% faster for the new simulation techniques than for basic block
dynamic binary translation based simulation and 14.8 times faster than interpretive
simulation. The average cycle-approximate simulation speed is shown to be at least
32% faster for the new simulation techniques than for basic block dynamic binary
translation based simulation and 8.37 times faster than cycle-accurate interpretive simulation.|
|Keywords: ||simulation speeds|
novel processor architecture
Dynamic binary translation based simulators
|Appears in Collections:||Informatics thesis and dissertation collection|
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